The present invention relates to integrated nonvolatile memories.
FIG. 1A is a circuit diagram of a “virtual ground” electrically programmable read only memory array (EPROM) described in W. D. Brown et al., “Nonvolatile Semiconductor Memory Technology” (IEEE Press, 1998), pages 33-35, incorporated herein by reference. FIG. 1B is a top view of the array, and FIG. 1C shows a vertical cross section A-A′ (FIG. 1B) passing through a wordline 104. Each memory cell 110 is a floating gate transistor. The floating gates 120 (FIGS. 1B, 1C), made of doped polysilicon, overlie P type silicon substrate 130 (FIGS. 1C) and are insulated from the substrate by a silicon dioxide layer 140. Control gates 104 are provided by doped polysilicon wordlines. Numeral 104 denotes both the wordlines and the control gates. Each wordline 104 runs through the array in the row direction (horizontal direction in FIGS. 1A-1C). Wordlines 104 are insulated from floating gates 120 and substrate 130 by dielectric 144. Bitlines 160 are diffused regions, doped N+, in substrate 130. Each bitline traverses the array in the column direction (vertically in FIGS. 1A, 1B). Each transistor 110 has its source/drain regions provided by the adjacent bitlines 160. Channel region 170 under the floating gate 120 is a P type region extending between the source/drain regions in substrate 130.
Bitlines 160 are connected to a circuit 180 which performs bitline selection, driving and sensing as needed for the memory operation. Wordline driving circuitry (not shown) is also provided.
Cell 110 is programmed by channel hot electron injection. During the programming, the cell's wordline 104 is at a high voltage (12V), one of the cell's source/drain regions 160 (one of the bitlines) is at 8˜9V, and the other source/drain region is grounded. To read the cell, the corresponding wordline is driven to 5V, one of the corresponding bitlines 160 is driven to 2V, and the other bitline is grounded. The array is erased by ultraviolet light.